Previous digital modulator systems of the phase shift keyed type (PSK) or the differential phase shift keyed type (DPSK) have employed phase changes in a sine wave carrier frequency to encode digital logic levels. These previous systems have required a phase coherent reference frequency at their demodulator for comparison of phases of the incoming modulated carrier frequency with the phase coherent reference frequency. Error can be introduced by relative drifts of the master oscillator at transmitter or receiver or can be due to phase drift or fluctuation in the propagation path. In DPSK information is encoded differentially in terms of phase change between successive bits but a coherent detector is still required where one input is the current bit and the other input the previous bit. The clock frequency for these systems, necessary for demodulation of signals to logic levels is derived in some previous systems from the carrier; in others by using an edge detector of the digital one pulse rise and fall to synchronize a phase lock loop. In the latter case the digital word length is limited and stop bits of digital ones are required to keep the clock frequency synchronized in the event of a string of digital zeros. In these systems, the start of a bit is denoted by the start of a phase period which coincides with a clock period of time. One previous DSPK system called Manchester Coding inserts a phase transition in the center of every bit in addition to the transitions of DPSK, thus supplying clock synchronization pulses in every bit.